Static memory cells in certain environments in which radiation is present such as communication satellite orbital space, can be susceptible to short pulsed transient dose radiation such as gamma dot or short high pulsed gamma radiation. A more detailed explanation of the transient dose problem follows, but first, background information shall be given with respect to the structure and operation of a static memory cell with reference to FIG. 1 which illustrates a schematic drawing of a conventional CMOS (complementary metal oxide semiconductor) static memory cell, typically used in a static random access memory (SRAM). Memory cell 2 is constructed according to well known methods of cross-coupled inverter realization and thus CMOS inverters are used in memory cell 2. A first CMOS inverter 4 in memory cell 2 comprises p-channel transistor 6 and n-channel transistor 8 having their source-to drain paths connected in series between Vdd and ground, and having their gates tied together. The second CMOS inverter 5 in memory cell 2 is similarly constructed, with p-channel transistor 10 and n-channel transistor 12 having their source-to-drain paths connected in series between Vdd and ground and their gates are also common. The cross-coupling is accomplished by the gates of transistor 6 and 8 being connected to the drains of transistor 10 and 12 (node S1), and by the gates of transistors 10 and 12 being connected to the drains of transistors 6 and 8 (node S2). N-channel pass transistor 14 has its source-to-drain path connected between node S2 and a first bit line BL, and has its gate connected to word line WL. N-channel pass transistor 16 similarly has its source-to drain path connected between node S1 and a second bit line BL--, and has its gate also connected to word line WL. Pass transistors 14, 16 when enabled, allow data to pass into and out of memory cell 2 from bit lines BL and BL--respectively. Bit lines BL and BL carry data into and out of memory cell 2. Pass transistors 14, 16 are enabled by word line WL which is a function of the row address in an SRAM. The row address is decoded by a row (not shown) decoder in the SRAM such that one out of n word lines is enabled, where n is the number of rows of memory cells in the memory which is a function of memory density and architecture.
In operation, the voltages of nodes S1 and S2 will necessarily be logical complements of one another, due to the cross-coupled nature of CMOS inverters 4,5 within memory cell 2. When word line WL is energized by the row decoder (not shown), according to the row address received at address inputs to an address buffer (not shown) connected to the row decoder, pass transistors 14 and 16 will be turned on, coupling nodes S1 and S2 to bit lines BL and BL--, respectively. Accordingly, when word line WL is high, the state of memory cell 2 can establish a differential voltage on BL and BL--. Alternatively, peripheral circuitry forcing a voltage on BL and BL-- can alter the state of memory cell 2. The sizes of the transistors shown in FIG. 1 are generally chosen such that when pass transistors 14 and 16 are turned on by word line WL, a differentially low voltage at bit line BL-- with respect to bit line BL can force node S1 to a logic low level. However, the sizes of the transistors shown in FIG. 1 are also chosen such that when transistors 14 and 16 are on, a differentially high voltage at bit line B with respect to bit line BL-- will not force node S2 high, nor will a differentially high voltage at bit line BL with respect to bit line BL force node S1 high. Therefore writing into memory cell 2 is accomplished by pulling the desired bit line and thus the desired side of cell 2 at either node S1 or node S2 low, which in turn due to feedback paths in cell 2, causes the opposite side of cell 2 to have a logic high state.
High short pulsed transient dosed radiation creates electron-hole pairs which get collected by electromagnetic fields within cell 2. This produces photo-current within cell 2 which can produce changes in voltages throughout the cell. Restated, the photo-current can cause logic upset in the memory. Note that the short pulsed transient dosed radiation such as gamma dot, is different from single event upset (SEU). One very distinct difference between these two situations is that for SEU only one node of a transistor is initially affected by radiation causing either the high node to go low or the low node high in voltage such that changes in voltage propagate through an associated memory cell. On the other hand for gamma dot, all transistors are affected. Furthermore, for gamma dot, whether the high or low node is affected more than the other is dependent upon the relative widths of the transistor attached to the nodes.
A reed therefore exists to harden static memory cells against short pulsed transient dose radiation.